Invention Grant
- Patent Title: Vertical CMOS structure and method
- Patent Title (中): 垂直CMOS结构和方法
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Application No.: US14640295Application Date: 2015-03-06
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Publication No.: US09472551B2Publication Date: 2016-10-18
- Inventor: Richard Kenneth Oxland
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/16 ; H01L29/20 ; H01L29/10 ; H01L21/02 ; H01L21/8258 ; H01L29/66

Abstract:
A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g. germanium) and an upper portion of another type of semiconductor (e.g. indium arsenide. The lower portion of the column provides a channel region for a transistor of one type, while the upper column provides a channel region for a transistor of another type. This provides a complementary pair that occupies a minimum of integrated circuit surface area. The complementary transistors can be utilized in a variety of circuit configurations. Described are complementary transistors where the lower transistor is p-type and the upper transistor is n-type.
Public/Granted literature
- US20160240533A1 VERTICAL CMOS STRUCTURE AND METHOD Public/Granted day:2016-08-18
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