Invention Grant
- Patent Title: Semiconductor Fin FET device with epitaxial source/drain
- Patent Title (中): 具有外延源极/漏极的半导体鳍FET器件
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Application No.: US14846414Application Date: 2015-09-04
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Publication No.: US09472669B1Publication Date: 2016-10-18
- Inventor: Hung-Li Chiang , Cheng-Yi Peng , Jyh-Cherng Sheu , Yee-Chia Yeo
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/78 ; H01L27/088 ; H01L21/8234 ; H01L29/66

Abstract:
In a method of fabricating a Fin FET, first and second fin structures are formed. The first and second fin structures protrude from an isolation insulating layer. A gate structure is formed over the first and second fin structures, each of which has source/drain regions, having a first width, outside of the gate structure. Portions of sidewalls of the source/drain regions are removed to form trimmed source/drain regions, each of which has a second width smaller than the first width. A strain material is formed over the trimmed source/drain regions such that the strain material formed on the first fin structure is separated from that on the second fin structure. An interlayer dielectric layer is formed over the gate structure and the source/drain regions with the strain material. A contact layer is formed on the strain material such that the contact layer wraps around the strain material.
Information query
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