Invention Grant
- Patent Title: Reducing loadline impedance in a system
- Patent Title (中): 降低系统中的负载线阻抗
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Application No.: US14154291Application Date: 2014-01-14
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Publication No.: US09478488B2Publication Date: 2016-10-25
- Inventor: Damion T. Searls , Edward P. Osburn
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop Pruner & Hu, P.C.
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/14 ; H01L23/498 ; H05K1/02 ; H05K1/18
Abstract:
In one embodiment, the present invention includes a semiconductor device mounted to a first side of a circuit board; and at least one voltage regulator device mounted to a second side of the circuit board, the second side opposite to the first side. Examples of the voltage regulator devices include output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.
Public/Granted literature
- US20140124942A1 Reducing Loadline Impedance in a System Public/Granted day:2014-05-08
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