Invention Grant
- Patent Title: Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer
- Patent Title (中): 具有凹陷电介质侧壁的半导体结构及其通过各向同性蚀刻阻挡介电层来制造的方法
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Application No.: US14600226Application Date: 2015-01-20
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Publication No.: US09478558B2Publication Date: 2016-10-25
- Inventor: Sateesh Koka , Senaka Kanakamedala , Raghuveer S. Makala , Rahul Sharangpani , Yanli Zhang , Yao-Sheng Lee , George Matamis
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/115 ; H01L21/28 ; H01L29/788 ; H01L21/311 ; H01L29/66

Abstract:
A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.
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