Invention Grant
- Patent Title: High performance interconnect link layer
- Patent Title (中): 高性能互连链路层
-
Application No.: US13976947Application Date: 2013-03-28
-
Publication No.: US09479196B2Publication Date: 2016-10-25
- Inventor: Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- International Application: PCT/US2013/034341 WO 20130328
- International Announcement: WO2014/065884 WO 20140501
- Main IPC: H03M13/09
- IPC: H03M13/09 ; H03M13/00 ; G06F13/42 ; G06F13/00 ; H04L12/46

Abstract:
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
Public/Granted literature
- US20140115420A1 HIGH PERFORMANCE INTERCONNECT LINK LAYER Public/Granted day:2014-04-24
Information query
IPC分类: