Invention Grant
- Patent Title: Parallel data switch
- Patent Title (中): 并行数据切换
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Application No.: US13072612Application Date: 2011-03-25
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Publication No.: US09479458B2Publication Date: 2016-10-25
- Inventor: Coke S. Reed , David Murphy
- Applicant: Coke S. Reed , David Murphy
- Agency: Meyertons Hood Kivlin Kowert & Goetzel, P.C.
- Agent Jeffrey C. Hood; Michael B. Davis
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/937 ; H04L12/933 ; H04L12/775 ; H04L12/773

Abstract:
An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.
Public/Granted literature
- US20150023367A1 PARALLEL DATA SWITCH Public/Granted day:2015-01-22
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