Invention Grant
- Patent Title: Intrinsic vertical bit line architecture
- Patent Title (中): 内在垂直位线架构
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Application No.: US14715562Application Date: 2015-05-18
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Publication No.: US09484092B2Publication Date: 2016-11-01
- Inventor: Perumal Ratnam
- Applicant: SANDISK 3D LLC
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G06F11/10 ; H01L27/24 ; H01L29/786 ; H01L45/00 ; G11C16/08 ; G11C16/10 ; G11C16/24 ; G11C16/26 ; G11C7/12 ; G11C7/18 ; G11C29/02 ; G11C29/12

Abstract:
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
Public/Granted literature
- US20160019952A1 INTRINSIC VERTICAL BIT LINE ARCHITECTURE Public/Granted day:2016-01-21
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