Invention Grant
- Patent Title: Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same
- Patent Title (中): 集成电路包括铜线上的选择性沉积的金属覆盖层及其制造方法
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Application No.: US14150428Application Date: 2014-01-08
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Publication No.: US09484252B2Publication Date: 2016-11-01
- Inventor: Moosung Chae , Larry Zhao
- Applicant: GLOBAL FOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Lorenz & Kopf, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L23/532 ; H01L23/528 ; H01L21/3213
Abstract:
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal capping layer on first sidewalls of a copper line while leaving exposed portions of a dielectric layer that are laterally adjacent to the copper line exposed. An ILD layer is deposited overlying the metal capping layer and the exposed portions of the dielectric layer.
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Information query
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