Invention Grant
- Patent Title: Stressed channel bulk fin field effect transistor
- Patent Title (中): 强调通道体散射场效应晶体管
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Application No.: US14881856Application Date: 2015-10-13
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Publication No.: US09484262B2Publication Date: 2016-11-01
- Inventor: Veeraraghavan S. Basker , Akira Hokazono , Hiroshi Itokawa , Tenko Yamashita , Chun-chen Yeh
- Applicant: International Business Machines Corporation , Kabushiki Kaisha Toshiba
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Steven J. Meyers
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L21/308 ; H01L21/8234 ; H01L27/088

Abstract:
Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
Public/Granted literature
- US20160035626A1 STRESSED CHANNEL BULK FIN FIELD EFFECT TRANSISTOR Public/Granted day:2016-02-04
Information query
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