Invention Grant
- Patent Title: Interconnect structures for wafer level package and methods of forming same
- Patent Title (中): 晶圆级封装的互连结构及其形成方法
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Application No.: US14464487Application Date: 2014-08-20
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Publication No.: US09484285B2Publication Date: 2016-11-01
- Inventor: Meng-Tse Chen , Chih-Wei Lin , Hui-Min Huang , Ming-Da Cheng , Chung-Shi Liu , Chen-Hua Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L21/48 ; H01L23/48 ; H01L23/31 ; H01L23/00
Abstract:
A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the die. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of the die.
Public/Granted literature
- US20160056056A1 Interconnect Structures for Wafer Level Package and Methods of Forming Same Public/Granted day:2016-02-25
Information query
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