Invention Grant
US09484405B1 Stacked nanowire devices formed using lateral aspect ratio trapping
有权
使用横向纵横比捕获形成堆叠的纳米线器件
- Patent Title: Stacked nanowire devices formed using lateral aspect ratio trapping
- Patent Title (中): 使用横向纵横比捕获形成堆叠的纳米线器件
-
Application No.: US14869118Application Date: 2015-09-29
-
Publication No.: US09484405B1Publication Date: 2016-11-01
- Inventor: Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Louis J. Percello
- Main IPC: H01L29/775
- IPC: H01L29/775 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/786 ; H01L21/02

Abstract:
A method for manufacturing a semiconductor device comprises depositing alternating layers of a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate in a stacked configuration, forming one or more first openings in the stacked configuration to a depth penetrating below an upper surface of a bottom second dielectric layer of the plurality of second dielectric layers, forming one or more second openings in the stacked configuration to a depth corresponding to an upper surface of the substrate or below an upper surface of the substrate, removing the plurality of second dielectric layers from the stacked configuration to form a plurality of gaps, and epitaxially growing a semiconductor material from a seed layer in the one or more second openings to fill the one or more first and second openings and the plurality of gaps, wherein defects caused by a lattice mismatch between the epitaxially grown semiconductor material and a material of the substrate are contained at a bottom portion of the one or more second openings.
Information query
IPC分类: