Invention Grant
US09484406B1 Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications
有权
用于制造用于半导体应用的器件的水平栅极的纳米线的方法
- Patent Title: Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications
- Patent Title (中): 用于制造用于半导体应用的器件的水平栅极的纳米线的方法
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Application No.: US14874146Application Date: 2015-10-02
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Publication No.: US09484406B1Publication Date: 2016-11-01
- Inventor: Shiyu Sun , Naomi Yoshida , Bingxi Wood
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/06 ; H01L21/02 ; H01L29/165 ; H01L29/41

Abstract:
The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.
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