Invention Grant
US09484924B2 Negative capacitance logic device, clock generator including the same and method of operating clock generator
有权
负电容逻辑器件，时钟发生器包括相同的操作时钟发生器和方法
- Patent Title: Negative capacitance logic device, clock generator including the same and method of operating clock generator
- Patent Title (中): 负电容逻辑器件，时钟发生器包括相同的操作时钟发生器和方法
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Application No.: US14614884Application Date: 2015-02-05
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Publication No.: US09484924B2Publication Date: 2016-11-01
- Inventor: Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
- Applicant: Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
- Applicant Address: KR Daejeon
- Assignee: Korea Advanced Institute of Science and Technology
- Current Assignee: Korea Advanced Institute of Science and Technology
- Current Assignee Address: KR Daejeon
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Priority: KR10-2015-0008700 20150119
- Main IPC: H03K3/315
- IPC: H03K3/315 ; H03L7/26 ; H03K19/16 ; H03K19/0185 ; H03B15/00 ; H01L29/66 ; B82Y25/00 ; H01L43/02 ; G11C11/16 ; H01L43/10
Abstract:
A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.
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