Invention Grant
- Patent Title: Circuit arrangement and method for calibrating activation signals for voltage-controlled oscillators
- Patent Title (中): 用于校准压控振荡器的激活信号的电路布置和方法
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Application No.: US14552173Application Date: 2014-11-24
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Publication No.: US09484929B2Publication Date: 2016-11-01
- Inventor: Heinz Werker
- Applicant: SILICON LINE GMBH
- Applicant Address: DE Munich
- Assignee: Silicon Line GmbH
- Current Assignee: Silicon Line GmbH
- Current Assignee Address: DE Munich
- Agency: Studebaker & Brackett PC
- Priority: DE102012104472 20120523
- Main IPC: H03B5/12
- IPC: H03B5/12 ; H03L7/00 ; H04L7/033 ; H03L7/18 ; H03B1/00 ; H03L7/08 ; H03L7/085 ; H03L7/099

Abstract:
In order to develop a circuit arrangement and also a method for calibrating at least one activation signal provided for a voltage-controlled oscillator such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed—that the respective number of clock cycles for at least one calibration oscillator and at least one reference oscillator associated with the calibration oscillator is counted by means of at least one clock cycle counter connected downstream of the calibration oscillator and the reference oscillator and a clock error resulting from the difference between these two numbers of clock cycles is integrated and—that the clock error is converted by means of at least one digital-to-analog converter connected downstream of the clock counter into analog tuning signals from which the calibrated activation signal is derived.
Public/Granted literature
- US20150381185A1 CIRCUIT ARRANGEMENT AND METHOD FOR CALIBRATING ACTIVATION SIGNALS FOR VOLTAGE-CONTROLLED OSCILLATORS Public/Granted day:2015-12-31
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