A variable resistive memory device may include a memory region and controller. The memory region may include a plurality of unit memory cells each electrically connected between a word line and a bit line. The controller may perform a driving operation of the word line in response to a read command. The controller may perform a driving operation of a bit line to output cell data through the bit line substantially simultaneously with the driving operation of the word line. Each of the unit memory cell may include a variable resistive material.