A memory array (101) includes a plurality of twin cells (104), each of which is composed of a first memory element (102) and a second memory element (103) which are each electrically rewritable and configured to memorize binary data according to a difference in threshold voltages therebetween. A power supply control circuit (105), upon receiving a request for erasing data in a twin cell, increases both the threshold voltage of the first memory element (102) and the threshold voltage of the second memory element (103) during the pre-writing, and after the pre-writing, differentiates the voltage of a first bit line (BL) which is connected to the first memory element (102) and the voltage of a second bit line (/BL) which is connected to the second memory element (103) during the application of erase pulse.