An SRAM unit cell includes first to fourth fin structures. A first Fin FET is formed by a first gate electrode and a first fin structure. A second Fin FET is formed by a second gate electrode and the first fin structure. A third Fin FET is formed by the second gate electrode and a third fin structure. A fourth Fin FET is formed by a third gate electrode and a second fin structure. A fifth Fin FET is formed by a fourth gate electrode and the second fin structure. A sixth Fin FET is formed by the fourth gate electrode and a fourth fin structure. A first dummy fin structure is located adjacent the second Fin FET, and electrically connected to the first fin structure. A second dummy fin structure is adjacent to the fifth Fin FET, and electrically connected to the second fin structure.