Invention Grant
- Patent Title: Device architecture and method for improved packing of vertical field effect devices
-
Application No.: US14817010Application Date: 2015-08-03
-
Publication No.: US09496386B2Publication Date: 2016-11-15
- Inventor: Thomas E. Harrington, III , Robert Kuo-Chang Yang
- Applicant: D3 Semiconductor LLC
- Applicant Address: US TX Addison
- Assignee: D3 Semiconductor LLC
- Current Assignee: D3 Semiconductor LLC
- Current Assignee Address: US TX Addison
- Agency: Schultz & Associates, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/04 ; H01L29/66 ; H01L29/423 ; H01L21/265 ; H01L29/739 ; H01L29/06 ; H01L29/10

Abstract:
A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
Public/Granted literature
- US20150340454A1 DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIELD EFFECT DEVICES Public/Granted day:2015-11-26
Information query
IPC分类: