Invention Grant
- Patent Title: Via resistance analysis systems and methods
- Patent Title (中): 通过电阻分析系统和方法
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Application No.: US13556129Application Date: 2012-07-23
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Publication No.: US09496853B2Publication Date: 2016-11-15
- Inventor: Wojciech Jakub Poppe , Puneet Gupta , Ilyas Elkin
- Applicant: Wojciech Jakub Poppe , Puneet Gupta , Ilyas Elkin
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: H03K3/03
- IPC: H03K3/03 ; G01R31/317 ; H01L21/66 ; G01R31/28

Abstract:
Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.
Public/Granted literature
- US20130021107A1 VIA RESISTANCE ANALYSIS SYSTEMS AND METHODS Public/Granted day:2013-01-24
Information query
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