Invention Grant
- Patent Title: Methods and apparatuses for reducing power consumption in a pattern recognition processor
- Patent Title (中): 用于降低模式识别处理器中的功耗的方法和装置
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Application No.: US12638751Application Date: 2009-12-15
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Publication No.: US09501705B2Publication Date: 2016-11-22
- Inventor: Harold B Noyes , David R. Brown
- Applicant: Harold B Noyes , David R. Brown
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G06F17/30
- IPC: G06F17/30 ; G06K9/00

Abstract:
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.
Public/Granted literature
- US20110145271A1 METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR Public/Granted day:2011-06-16
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