Invention Grant
- Patent Title: Two-step shallow trench isolation (STI) process
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Application No.: US14640991Application Date: 2015-03-06
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Publication No.: US09502280B2Publication Date: 2016-11-22
- Inventor: Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang-Hsiang Ko , Chen-Ming Huang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/762 ; H01L29/78 ; H01L21/8234 ; H01L29/66 ; H01L21/02 ; H01L21/033 ; H01L21/3105 ; H01L29/06

Abstract:
Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
Public/Granted literature
- US20150179502A1 Two-Step Shallow Trench Isolation (STI) Process Public/Granted day:2015-06-25
Information query
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