Invention Grant
US09502535B2 Semiconductor structure and etch technique for monolithic integration of III-N transistors
有权
用于III-N晶体管单片集成的半导体结构和蚀刻技术
- Patent Title: Semiconductor structure and etch technique for monolithic integration of III-N transistors
- Patent Title (中): 用于III-N晶体管单片集成的半导体结构和蚀刻技术
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Application No.: US15094985Application Date: 2016-04-08
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Publication No.: US09502535B2Publication Date: 2016-11-22
- Inventor: Ling Xia , Mohamed Azize , Bin Lu
- Applicant: Cambridge Electronics, Inc.
- Applicant Address: US MA Cambridge
- Assignee: Cambridge Electronics, Inc.
- Current Assignee: Cambridge Electronics, Inc.
- Current Assignee Address: US MA Cambridge
- Agency: American Patent Agency PC
- Agent Daniar Hussain; Xiaomeng Shi
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/088 ; H01L29/66
Abstract:
Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0≦x, y, z≦1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0
Public/Granted literature
- US20160300835A1 SEMICONDUCTOR STRUCTURE AND ETCH TECHNIQUE FOR MONOLITHIC INTEGRATION OF III-N TRANSISTORS Public/Granted day:2016-10-13
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