A circuit includes first and second gated buffers, respectively receiving and outputting logic signals, including a delayed signal. A finite state machine receives the delayed signal and a clock signal and assumes first or second machine states. The first gated buffer is conditionally enabled based on a state of the finite state machine, while the second gated buffer is enabled regardless of the state of the finite state machine. A method includes receiving and generating logic signals via first and second gated buffers, including a delayed signal. The method includes receiving the delayed signal and a clock signal in a finite state machine. The method further includes enabling the first gated buffer depending on whether the state machine is in a first or a second machine state, and enabling the second gated buffer when the finite state machine is either in the first or the second machine state.