Invention Grant
- Patent Title: Methods and apparatuses having strings of memory cells and select gates with double gates
- Patent Title (中): 具有存储单元串和双门选择门的方法和装置
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Application No.: US14031509Application Date: 2013-09-19
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Publication No.: US09508735B2Publication Date: 2016-11-29
- Inventor: Koji Sakui
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; G11C16/26 ; G11C16/04 ; G11C16/34
Abstract:
An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate. The front and back control gates can be coupled together such that they are biased at the same voltage or separate such that they can be biased at different voltages.
Public/Granted literature
- US20150078089A1 METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS AND SELECT GATES WITH DOUBLE GATES Public/Granted day:2015-03-19
Information query
IPC分类:
