Invention Grant
- Patent Title: Interference estimation circuit and method
- Patent Title (中): 干扰估算电路及方法
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Application No.: US11696303Application Date: 2007-04-04
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Publication No.: US09509366B2Publication Date: 2016-11-29
- Inventor: Chi-Yuan Peng , Chih-Chiu Wang
- Applicant: Chi-Yuan Peng , Chih-Chiu Wang
- Applicant Address: TW Hsin-Tien, Taipei
- Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee Address: TW Hsin-Tien, Taipei
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H04B1/707
- IPC: H04B1/707 ; H04B1/7097 ; H04L1/00

Abstract:
The present application provides an interference estimation circuit which includes a signal generator, a first symbol extractor and a first mixer. The signal generator generates an orthogonal signal orthogonal to partial symbols of a plurality of pilot signals. The first symbol extractor extracts partial symbols of a first decoded signal decoded from a received signal wherein the first decoded signal contains one of the plurality of pilot signals, and includes an input node for receiving the first decoded signal and an output node for outputting a first extracted signal. The first extracted signal is substantially orthogonal to the orthogonal signal. The first mixer is coupled to the signal generator for receiving the orthogonal signal and to the first symbol extractor for receiving the first extracted signal, and outputs a first mixed signal of the orthogonal signal and the first extracted signal for interference estimation.
Public/Granted literature
- US20080247472A1 INTERFERENCE ESTIMATION CIRCUIT AND METHOD Public/Granted day:2008-10-09
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