Invention Grant
- Patent Title: Fast scheduling and optmization of multi-stage hierarchical networks
- Patent Title (中): 快速调度和多阶段分层网络的优化
-
Application No.: US14329876Application Date: 2014-07-11
-
Publication No.: US09509634B2Publication Date: 2016-11-29
- Inventor: Venkat Konda
- Applicant: Konda Technologies Inc.
- Applicant Address: US CA San Jose
- Assignee: Konda Technologies Inc.
- Current Assignee: Konda Technologies Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H04L12/933
- IPC: H04L12/933

Abstract:
Significantly optimized multi-stage networks with scheduling methods for faster scheduling of connections, useful in wide target applications, with VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each block employ several slices of rings of stages of switches with inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand side only, or from both left-hand side and right-hand side; and employ multi-drop links where outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are connected to either inlet links of switches in the another stage of a ring in the same or another sub-integrated circuit block.
Public/Granted literature
- US20150049768A1 FAST SCHEDULING AND OPTMIZATION OF MULTI-STAGE HIERARCHICAL NETWORKS Public/Granted day:2015-02-19
Information query