Invention Grant
- Patent Title: Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components
- Patent Title (中): 具有互连层的半导体器件包括与金属部件交错的电介质段
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Application No.: US14706311Application Date: 2015-05-07
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Publication No.: US09520362B2Publication Date: 2016-12-13
- Inventor: Chun-Chieh Lin , Hung-Wen Su , Ming-Hsing Tsai , Syun-Ming Jang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/522 ; H01L29/51 ; H01L23/532

Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
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Information query
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