Invention Grant
US09524237B2 Data processing device and semiconductor intergrated circuit device for a bi-endian system
有权
用于双端系统的数据处理设备和半导体集成电路器件
- Patent Title: Data processing device and semiconductor intergrated circuit device for a bi-endian system
- Patent Title (中): 用于双端系统的数据处理设备和半导体集成电路器件
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Application No.: US13063347Application Date: 2009-05-28
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Publication No.: US09524237B2Publication Date: 2016-12-20
- Inventor: Naoshi Ishikawa , Seiji Ikari , Hiromi Nagayama
- Applicant: Naoshi Ishikawa , Seiji Ikari , Hiromi Nagayama
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-234768 20080912
- International Application: PCT/JP2009/059738 WO 20090528
- International Announcement: WO2010/029794 WO 20100318
- Main IPC: G06F12/04
- IPC: G06F12/04 ; G06F9/30

Abstract:
The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.
Public/Granted literature
- US20110191569A1 DATA PROCESSING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2011-08-04
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