Provided is a technique for promoting miniaturization of a MISFET. A p-type well region is disposed between LDDs (n-type low-concentration regions) of a MISFET (Qn) to cause both the well region and the low-concentration region to partially overlap each other, whereby an overlap region formed of an n-type semiconductor region having a higher resistance than that of the n-type low-concentration region is provided between the p-type well region and each of the n-type low-concentration regions. In this way, the overlap region can relieve an electric field concentration at the end of the n-type low-concentration region, thereby suppressing the occurrence of hot carriers without elongating an offset length of the LDD, which can promote the miniaturization of the MISFET (Qn), particularly, that operates at high voltage.