Invention Grant
- Patent Title: Semiconductor integrated circuit device with reduced leakage current
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Application No.: US14826911Application Date: 2015-08-14
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Publication No.: US09530485B2Publication Date: 2016-12-27
- Inventor: Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kanagawa
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Kanagawa
- Agency: Stites & Harbison, PLLC
- Agent Stephen J. Weyer, Esq.
- Priority: JP2001-168945 20010605; JP2002-17840 20020128
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/412 ; G11C11/418 ; H01L21/8234 ; H01L21/8238 ; H01L27/088 ; H01L27/092 ; H01L27/105 ; H01L27/11 ; H03K19/00 ; G11C11/413

Abstract:
The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
Public/Granted literature
- US20150357026A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE CURRENT Public/Granted day:2015-12-10
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