Invention Grant
- Patent Title: EEPROM memory cell gate control signal generating circuit
- Patent Title (中): EEPROM存储单元门控制信号发生电路
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Application No.: US14976710Application Date: 2015-12-21
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Publication No.: US09530505B1Publication Date: 2016-12-27
- Inventor: Guoyou Feng , Yanli Zhao
- Applicant: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
- Applicant Address: CN Shanghai
- Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Current Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
- Current Assignee Address: CN Shanghai
- Agency: MKG, LLC
- Priority: CN201510315395 20150610
- Main IPC: G11C16/08
- IPC: G11C16/08 ; G11C16/10 ; G11C16/24 ; G11C16/12 ; G11C16/14 ; G11C16/26 ; G11C16/16 ; G11C5/06 ; G11C16/30

Abstract:
An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits; the output of the high-voltage row decoding circuit is divided into two routes, which output a first total wordline voltage used for providing the erasing positive voltage and a second total wordline voltage used for providing the erasing negative voltage, respectively; besides, the two-route voltages are inputted into the individual word selection circuits respectively, which avoids the influence of the erasing positive voltage on the grid oxide layer of an NMOS transistor and the influence of the erasing negative voltage on a PMOS transistor, and can save the MOS transistor used for isolating the grid oxide layer.
Public/Granted literature
- US20160365148A1 EEPROM MEMORY CELL GATE CONTROL SIGNAL GENERATING CIRCUIT Public/Granted day:2016-12-15
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