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US09533494B2 Address architecture for fluid ejection chip 有权
流体喷射芯片的地址架构

Address architecture for fluid ejection chip
Abstract:
A printhead including one or more fluid vias in fluid communication with a fluid supply, each of the one or more fluid vias being associated with a first number of heating elements, the heating elements being divided into groups of a second number of heating elements so as to form a number of primitive groups, and an electrical interface having at least one shift register that receives primitive address data to allow for selective application of electrical signals to the heating elements so that fluid is ejected from the printhead in accordance with image data, the number of primitive groups being dependent on the print resolution of the printhead so that a number of bits required for the at least one shift register to address each heater is independent of the print resolution of the printhead.
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