Performing RC analysis in a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design, the hierarchical circuit data comprising top-level data and lower-level block data; obtaining hierarchical RC information; combining RC information on boundary paths between blocks and RC information on boundary paths within blocks to generate boundary RC information; performing RC analysis using the boundary RC information to determine a timing delay; and comparing the timing delay with a desired delay to determine whether an RC timing is closed.