Invention Grant
- Patent Title: Gate pad and gate feed breakdown voltage enhancement
- Patent Title (中): 栅极和栅极馈电击穿电压增强
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Application No.: US15042988Application Date: 2016-02-12
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Publication No.: US09536941B2Publication Date: 2017-01-03
- Inventor: Kenji Sugiura , Takeshi Ishiguro
- Applicant: Michael W. Shore
- Applicant Address: US TX Dallas
- Assignee: Michael Wayne Shore
- Current Assignee: Michael Wayne Shore
- Current Assignee Address: US TX Dallas
- Agency: Panitch Schwarze Belisario & Nadel LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/423 ; H01L29/10
Abstract:
A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers.
Public/Granted literature
- US20160163787A1 GATE PAD AND GATE FEED BREAKDOWN VOLTAGE ENHANCEMENT Public/Granted day:2016-06-09
Information query
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