Invention Grant
US09536983B2 Methods of manufacturing semiconductor devices including gate patterns with sidewall spacers and capping patterns on the sidewall spacers
有权
制造半导体器件的方法,其包括具有侧壁间隔物的栅极图案和侧壁间隔物上的封盖图案
- Patent Title: Methods of manufacturing semiconductor devices including gate patterns with sidewall spacers and capping patterns on the sidewall spacers
- Patent Title (中): 制造半导体器件的方法,其包括具有侧壁间隔物的栅极图案和侧壁间隔物上的封盖图案
-
Application No.: US14970710Application Date: 2015-12-16
-
Publication No.: US09536983B2Publication Date: 2017-01-03
- Inventor: Doo-Young Lee , Dohyoung Kim , Johnsoo Kim , Heungsik Park , Hongsik Shin , Younghun Choi
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel, P.A.
- Priority: KR10-2015-0020255 20150210
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/423 ; H01L29/40

Abstract:
A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.
Public/Granted literature
- US20160233310A1 Methods of Manufacturing Semiconductor Devices Including Gate Patterns with Sidewall Spacers Public/Granted day:2016-08-11
Information query
IPC分类: