Invention Grant
US09537469B2 CMOS level shifter with reduced high voltage transistor count 有权
具有降低高压晶体管数量的CMOS电平移位器

CMOS level shifter with reduced high voltage transistor count
Abstract:
A digital level shifter adapted to shift an input signal from switching in a low voltage range, to an output switching in a high voltage range has a glitch generator configured to generate pulses at rising and falling transitions of the input signal. Glitch generator output triggers a multiple-level current source to a high current mode, operating in a low current mode at other times. The current source feeds a differential pair of high voltage transistors with a first transistor of the pair having a gate coupled to the input signal and a second transistor of the pair having a gate coupled to a complement of the input signal. An active load and buffer circuit receives current from the differential pair and drives the output accordingly.
Public/Granted literature
Information query
Patent Agency Ranking
0/0