Invention Grant
- Patent Title: CMOS level shifter with reduced high voltage transistor count
- Patent Title (中): 具有降低高压晶体管数量的CMOS电平移位器
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Application No.: US15034814Application Date: 2014-11-06
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Publication No.: US09537469B2Publication Date: 2017-01-03
- Inventor: Neaz Farooqi , Glenn E. Noufer , Randall L. Sandusky
- Applicant: TREEHOUSE DESIGN, INC. , Neaz Farooqi , Glenn E. Noufer , Randall L. Sandusky
- Applicant Address: US CO Colorado Springs
- Assignee: Treehouse Design, Inc.
- Current Assignee: Treehouse Design, Inc.
- Current Assignee Address: US CO Colorado Springs
- Agency: Lathrop & Gage LLP
- International Application: PCT/US2014/064358 WO 20141106
- International Announcement: WO2015/069903 WO 20150514
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K3/012 ; H03K19/0185

Abstract:
A digital level shifter adapted to shift an input signal from switching in a low voltage range, to an output switching in a high voltage range has a glitch generator configured to generate pulses at rising and falling transitions of the input signal. Glitch generator output triggers a multiple-level current source to a high current mode, operating in a low current mode at other times. The current source feeds a differential pair of high voltage transistors with a first transistor of the pair having a gate coupled to the input signal and a second transistor of the pair having a gate coupled to a complement of the input signal. An active load and buffer circuit receives current from the differential pair and drives the output accordingly.
Public/Granted literature
- US20160294370A1 A CMOS LEVEL SHIFTER WITH REDUCED HIGH VOLTAGE TRANSISTOR COUNT Public/Granted day:2016-10-06
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