A method includes sampling an input voltage signal applied to an ADC, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining in a search logic block a digital code representation for the comparison result. The method may also include performing a calibration by: performing an additional cycle, wherein a last comparison carried out for determining a least significant bit of the digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode, so obtaining an additional comparison; determining from a difference between results of the additional comparison and the last comparison a sign of a comparator offset error between the comparator resolution modes; and tuning, in accordance with a sign of the comparator offset error, a programmable capacitor connected at an input of the comparator, thereby inducing a voltage step to counteract the comparator offset error.