Invention Grant
- Patent Title: Staggered parity
- Patent Title (中): 交错平价
-
Application No.: US14564195Application Date: 2014-12-09
-
Publication No.: US09537608B2Publication Date: 2017-01-03
- Inventor: Shahab Oveis Gharan , James Harley , Kim B. Roberts
- Applicant: Shahab Oveis Gharan , James Harley , Kim B. Roberts
- Applicant Address: US MD Hanover
- Assignee: CIENA CORPORATION
- Current Assignee: CIENA CORPORATION
- Current Assignee Address: US MD Hanover
- Agency: Integral Intellectual Property Inc.
- Agent Miriam Paton
- Main IPC: G06F11/00
- IPC: G06F11/00 ; H03M13/00 ; H04L1/00 ; G06F11/10 ; H03M13/29 ; H03M13/15

Abstract:
In a Forward Error Correction (FEC) technique, parity vectors are computed such that: each parity vector spans a set of frames; a subset of bits of each frame is associated with parity bits in each parity vector; and a location of parity bits associated with one frame in one parity vector is different from that of parity bits associated with the frame in another parity vector. Values of decoded bits of a first frame are deduced from known parity bits of a first parity vector having an effective length of one frame. For parity vectors having, an effective length greater than one frame, a Log Likelihood Ratio of each unknown parity bit associated with the first frame is updated based on known and unknown parity bits of each parity vector. The first frame is decoded using the deduced bit values and the updated LLR values.
Public/Granted literature
- US20160164632A1 STAGGERED PARITY Public/Granted day:2016-06-09
Information query