Invention Grant
- Patent Title: Semiconductor integrated circuit and method of processing in semiconductor integrated circuit
- Patent Title (中): 半导体集成电路和半导体集成电路中的处理方法
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Application No.: US14287635Application Date: 2014-05-27
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Publication No.: US09542266B2Publication Date: 2017-01-10
- Inventor: Chikahiro Deguchi , Yutaka Sekino , Yoshiki Okumura , Hiroaki Watanabe , Naoki Maezawa , Hideyuki Negi
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2013-124784 20130613
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H04L1/00 ; G06F11/22 ; H03M13/09 ; H03M13/11 ; H03M13/29 ; G06F11/08 ; G06F11/14 ; H03M13/05 ; G06F11/16

Abstract:
A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.
Public/Granted literature
- US20140372837A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PROCESSING IN SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2014-12-18
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