Invention Grant
US09542353B2 System and method for reducing command scheduling constraints of memory circuits
有权
用于减少存储器电路的命令调度约束的系统和方法
- Patent Title: System and method for reducing command scheduling constraints of memory circuits
- Patent Title (中): 用于减少存储器电路的命令调度约束的系统和方法
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Application No.: US11929225Application Date: 2007-10-30
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Publication No.: US09542353B2Publication Date: 2017-01-10
- Inventor: Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
- Applicant: Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
- Applicant Address: US CA Mountain View
- Assignee: Google Inc.
- Current Assignee: Google Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fish & Richardson P.C.
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/42 ; G06F13/28 ; G11C11/406 ; G11C11/4093
Abstract:
A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
Public/Granted literature
- US20080120443A1 SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS Public/Granted day:2008-05-22
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