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US09542643B2 Efficient hardware implementation of spiking networks 有权
高效的硬件实现spiking网络

Efficient hardware implementation of spiking networks
Abstract:
Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.
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