The transistor layer is disposed above or below the memory layer and includes a transistor. The wiring line layer connects the memory layer and the transistor layer. The memory cell array comprises a plurality of select gate lines connected to gates of a plurality of the select transistors aligned in a third direction. The wiring line layer comprises: a first connecting wiring line connected to a first select gate line of the plurality of select gate lines and extending in the third direction; and a second connecting wiring line connected to a second select gate line adjacent in a second direction to the first select gate line. This second connecting wiring line at least comprises: a first portion extending in the third direction; and a second portion extending from the first portion to a layer below the first connecting wiring line.