Invention Grant
US09543029B2 Non-volatile semiconductor memory device and reading method for non-volatile semiconductor memory device that includes charging of data latch input node prior to latching of sensed data 有权
用于非易失性半导体存储器件的非易失性半导体存储器件和读取方法,其包括在锁存感测数据之前对数据锁存器输入节点进行充电

  • Patent Title: Non-volatile semiconductor memory device and reading method for non-volatile semiconductor memory device that includes charging of data latch input node prior to latching of sensed data
  • Patent Title (中): 用于非易失性半导体存储器件的非易失性半导体存储器件和读取方法,其包括在锁存感测数据之前对数据锁存器输入节点进行充电
  • Application No.: US14820289
    Application Date: 2015-08-06
  • Publication No.: US09543029B2
    Publication Date: 2017-01-10
  • Inventor: Takuyo Kodama
  • Applicant: KABUSHIKI KAISHA TOSHIBA
  • Applicant Address: JP Tokyo
  • Assignee: Kabushiki Kaisha Toshiba
  • Current Assignee: Kabushiki Kaisha Toshiba
  • Current Assignee Address: JP Tokyo
  • Agency: Patterson & Sheridan, LLP
  • Priority: JP2014-161315 20140807
  • Main IPC: G11C16/04
  • IPC: G11C16/04 G11C16/06 G11C16/26 G11C16/32
Non-volatile semiconductor memory device and reading method for non-volatile semiconductor memory device that includes charging of data latch input node prior to latching of sensed data
Abstract:
A non-volatile semiconductor memory device includes a memory cell, and a sense amplifier that includes a latch unit, a first transistor having a first end electrically connected to the latch unit and a second end electrically connected to a first node, a second transistor having a first end electrically connected to the first node and a second end electrically connected to the memory cell, and a third transistor having a first end electrically connected to a second node between the first end of the first transistor and the latch unit. A control unit of the device controls the sense amplifier during a read operation, to charge the second node to a first voltage, and then charge the first node to a second voltage, turn on the second transistor after charging the first node to the second voltage, and turn on the third transistor after turning on the second transistor.
Public/Granted literature
Information query
Patent Agency Ranking
0/0