Invention Grant
US09543139B2 In-situ support structure for line collapse robustness in memory arrays
有权
存储阵列线路崩溃鲁棒性的原位支持结构
- Patent Title: In-situ support structure for line collapse robustness in memory arrays
- Patent Title (中): 存储阵列线路崩溃鲁棒性的原位支持结构
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Application No.: US14246656Application Date: 2014-04-07
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Publication No.: US09543139B2Publication Date: 2017-01-10
- Inventor: Akira Matsudaira , Donovan Lee
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus LLP
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L21/02 ; H01L21/28 ; H01L29/788 ; H01L27/02 ; H01L27/115

Abstract:
Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.
Public/Granted literature
- US20150287733A1 IN-SITU SUPPORT STRUCTURE FOR LINE COLLAPSE ROBUSTNESS IN MEMORY ARRAYS Public/Granted day:2015-10-08
Information query
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