Invention Grant
US09543159B2 Patterning process of a semiconductor structure with a wet strippable middle layer
有权
具有湿可剥离中间层的半导体结构的图案化过程
- Patent Title: Patterning process of a semiconductor structure with a wet strippable middle layer
- Patent Title (中): 具有湿可剥离中间层的半导体结构的图案化过程
-
Application No.: US14671552Application Date: 2015-03-27
-
Publication No.: US09543159B2Publication Date: 2017-01-10
- Inventor: Chien-Chih Chen , Chia-Wei Chen , Ching-Yu Chang , Shao-Jyun Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/02 ; H01L21/308 ; H01L21/266 ; H01L21/027 ; H01L21/32 ; H01L21/67

Abstract:
A lithography method is provided in accordance with some embodiments. The lithography method includes forming an under layer of a polymeric material on a substrate; forming a silicon-containing middle layer on the under layer, wherein the silicon-containing middle layer has a silicon concentration in weight percentage less than 20% and is wet strippable; forming a patterned photosensitive layer on the silicon-containing middle layer; performing a first etching process to transfer a pattern of the patterned photosensitive layer to the silicon-containing middle layer; performing a second etching process to transfer the pattern to the under layer; and performing a wet stripping process to the silicon-containing middle layer and the under layer.
Public/Granted literature
- US20160284557A1 Patterning Process of a Semiconductor Structure with a Wet Strippable Middle Layer Public/Granted day:2016-09-29
Information query
IPC分类: