Invention Grant
- Patent Title: Structure and method for forming interconnect structure
- Patent Title (中): 用于形成互连结构的结构和方法
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Application No.: US14593363Application Date: 2015-01-09
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Publication No.: US09543198B2Publication Date: 2017-01-10
- Inventor: Chih-Chien Chi , Huang-Yi Huang , Szu-Ping Tung , Ching-Hua Hsieh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L23/48 ; H01L23/482

Abstract:
A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void.
Public/Granted literature
- US20150123279A1 Structure and Method for Forming Interconnect Structure Public/Granted day:2015-05-07
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