Invention Grant
- Patent Title: Method for forming three-dimensional interconnection, circuit arrangement comprising three-dimensional interconnection, and metal film-forming composition for three-dimensional interconnection
- Patent Title (中): 用于形成三维互连的方法，包括三维互连的电路装置和用于三维互连的金属成膜组合物
-
Application No.: US14836236Application Date: 2015-08-26
-
Publication No.: US09543201B2Publication Date: 2017-01-10
- Inventor: Kenzou Ookita , Isao Aritome , Keisuke Kuriyama , Taichi Matsumoto , Kazuto Watanabe , Atsushi Kobayashi , Sugirou Shimoda
- Applicant: JSR Corporation
- Applicant Address: JP Minato-ku
- Assignee: JSR Corporation
- Current Assignee: JSR Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2014-173318 20140827; JP2014-173343 20140827
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/535 ; H01L23/522 ; H01L23/485 ; H01L23/498 ; H01L21/48 ; H01L21/288 ; H01L23/48 ; H01L23/14 ; H01L23/532
Abstract:
In a method for forming a three-dimensional interconnection, a contact plug is formed within a through hole provided in a substrate and an upper wire formed on an upper side of the substrate and a lower wire formed on a lower side are electrically connected to one another by the contact plug. A coating film is formed on an upper surface of the substrate and inner surface of the through hole by applying a metal film-forming composition containing at least one salt of and a particle of a metal to the substrate provided with the through hole. A metal film is formed by heating the coating film, and plated by filling up the through hole by depositing a conductor on the metal film by a plating process using the metal film as a seed layer. An excess conductor deposited in the plating is removed by a chemical mechanical polishing process.
Public/Granted literature
Information query
IPC分类:
