Invention Grant
US09543271B2 Semiconductor device having a sealing layer covering a semiconductor memory unit and a memory controller
有权
具有覆盖半导体存储单元的密封层和存储器控制器的半导体器件
- Patent Title: Semiconductor device having a sealing layer covering a semiconductor memory unit and a memory controller
- Patent Title (中): 具有覆盖半导体存储单元的密封层和存储器控制器的半导体器件
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Application No.: US14837997Application Date: 2015-08-27
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Publication No.: US09543271B2Publication Date: 2017-01-10
- Inventor: Manabu Matsumoto , Akira Tanimoto , Isao Ozawa
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2015-046517 20150309
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L25/03 ; H01L25/065 ; H01L25/00 ; H01L23/31 ; H01L23/00 ; H01L21/56
Abstract:
A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.
Public/Granted literature
- US20160268229A1 SEMICONDUCTOR DEVICE HAVING A SEALING LAYER COVERING A SEMICONDUCTOR MEMORY UNIT AND A MEMORY CONTROLLER Public/Granted day:2016-09-15
Information query
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