A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.