Invention Grant
US09547038B2 Low-overhead debug architecture using a speculative, concurrent and distributed data capture and propagation scheme
有权
低架构调试架构,采用推测性,并发和分布式数据捕获和传播方案
- Patent Title: Low-overhead debug architecture using a speculative, concurrent and distributed data capture and propagation scheme
- Patent Title (中): 低架构调试架构,采用推测性,并发和分布式数据捕获和传播方案
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Application No.: US14714283Application Date: 2015-05-16
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Publication No.: US09547038B2Publication Date: 2017-01-17
- Inventor: Rohit Natarajan
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G06F11/34

Abstract:
A system and corresponding method captures speculative and concurrent trace-data and trace-clock information from core processing units of a System on a Chip (SOC). An interface receives trace data from at least one core processing unit, and a storage array stores the trace data in two different modes of operation. In the first mode, which occurs prior to a predetermined operating state of the SOC, the storage array operates in a circular buffer mode in which the newest trace data overwrites the oldest trace data when the storage array becomes full In the second mode, which occurs after the predetermined operating state of the SOC, the storage array operates in a FIFO mode in which the newest trace data is written into the storage array and the oldest trace data contained in the storage array is output to a debug processing core unit of the SOC.
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